The steadily decreasing size and growing density and complexity of integrated circuit devices, such as processors, has made testing more difficult and costly. Therefore, modern integrated circuits usually incorporate a variety of design-for-test structures to enhance their inherent testability. Design-for-testability (DFT) refers to a technique for reducing the complexity associated with design testing by including test logic and access points for accessing such test logic within an integrated circuit device. Typically, the DFT structures are based on a scan design or an automatic test pattern generation (ATPG) design, where scan test or ATPG test data may be provided to a test pin or where a plurality of externally accessible scan chains may be embedded into the integrated circuit. Typically, scan test design is used in conjunction with fault simulation and combinational automatic test pattern generation to generate manufacturing and diagnostic test patterns for production test and prototype debug processes.
With respect to latch based memory devices such as, for example, register files, the standard or conventional test approach, namely a scan test with an ATPG pattern generation, is highly complex and cost inefficient. Therefore, latch based memory devices are tested either by functional bit patterns or by implementing additional hardware like, for example, memory built-in self-test (MBIST) structures. With functional bit patterns a significant additional programming effort as well as administrative effort in the work-out of test procedures and in the management of test runs will be necessary. Additional MBIST hardware requires additional development effort and additional space on the device. Moreover, the MBIST circuitry may cause additional leakage current and electrical power loss.